The field of invention relates to signal processing generally; and, more specifically, to a method and apparatus for a level shifter with a symmetrical output waveform.
FIG. 1a shows an embodiment of a differential to single ended level shifter 101. A level shifter 101 changes an electronic signal""s voltage level(s). Differential to single ended means the input signal is differential and the output signal is single ended. FIG. 1b shows an embodiment of a transistor level design for the level shifter 101 of FIG. 1a. FIG. 1c shows an exemplary differential input signal (IN+, INxe2x88x92) 102c, 103c and an exemplary single ended output signal (LS OUT)104c for the level shifter embodiment 101 of FIG. 1b. 
As observed with respect to the exemplary waveforms of FIG. 1c, the level shifter 101 output signal 104c provides the same logical information as the differential input signal 102c, 103c (IN+, INxe2x88x92) but with different voltage levels. That is, the input signals 102c and 103c (IN+ and INxe2x88x92) swing over a voltage range of xe2x80x9cAxe2x80x9d volts while the output signal 104c (LS OUT), in response, swings over a voltage range of xe2x80x9cVccxe2x80x9d voltsxe2x88x92where Vcc greater than A (noting that GND corresponds to 0.0 volts).
Different voltage swings (as between the input and output signals) correspond to the changing or xe2x80x9cshiftingxe2x80x9d of at least one input voltage level to a new output voltage level. The particular level shifter 101 that is shown in FIGS. 1a and 1b (and whose operation is demonstrated in FIG. 1c) may be referred to as a xe2x80x9crail-to-railxe2x80x9d level shifter because the output signal 104c (LS OUT) swings between the shifter""s supply rails of Vcc and GND. Rail-to-rail level shifters are often used for changing the levels of an electronic signal to better conform to those expected by digital circuitry (e.g., that is coupled to output 104a,b).
A problem with differential to single ended level shifters (including those of the rail-to-rail type) is the lack of symmetry between the rise times and fall times of the output signal waveform 104c (LS OUT). For example, referring to the exemplary output signal waveform 104c of FIG. 1c, note that the signal rise time T1 is less than the signal fall time T2. The asymmetry between rise and fall times arises from the asymmetry in the design of the level shifter.
That is, the conversion of a differential signal into a single ended signal involves asymmetrical processing. For example, referring to the exemplary transistor level embodiment of FIG. 1b and the exemplary waveforms 102c, 103c and 104c of FIG. 1c, note that a logic low INxe2x88x92 103c signal value corresponds to logic high LS OUT 104c signal value of Vcc. According to the design of FIG. 1b, the above described relationship between INxe2x88x92 and LS OUT is achieved by transistor Q2. Specifically, when INxe2x88x92 is a logic low Q2 turns xe2x80x9conxe2x80x9d which, in turn, effectively shorts the output node 104b to the Vcc rail.
Note also that a logic low IN+ 102c signal value corresponds to a logic low LS OUT 104c signal value. According to the design of FIG. 1b, the above described relationship between IN+ and LS OUT is achieved by transistors Q1, Q3 and Q4. Specifically, when IN+ is a logic low Q1 turns xe2x80x9conxe2x80x9d which results in the driving of current through Q3. The driving of current through Q3 raises the drain-to-source voltage across Q3 which, correspondingly, also raises the gate voltage on Q4. Raising the gate voltage on Q4 eventually turns xe2x80x9conxe2x80x9d Q4 which, in turn, effectively shorts the output node 104b to the GND rail.
Comparing the dynamics of how the output voltage rails of Vcc or GND are formed at the level shifter output node 104b, note that one transistor (Q2) is mostly involved with the raising of the output 104b LS OUT voltage to Vcc; while three transistors (Q1, Q3, Q4) are mostly involved with the lowering of the output 104 LS OUT voltage to GND. Because less transistors are involved with the raising of the output 104b LS OUT voltage than its lowering, the output 104b LS OUT voltage rises faster than it falls.
Hence, as mentioned above, the rise time T1 of the output signal waveform 104c LS OUT (of FIG. 1c) is less than its fall time T2. Problems may arise if a signal having an asymmetry (such as the level shifter output signal 104c LS OUT having the aforementioned difference between its rise and fall times) is processed or otherwise used. For example, data may be incorrectly interpreted.